<added comments to original text shown in light purple>
The ANTIC and CTIA chips generate the television display at the rate of 60 frames per second on the NTSC (US) system. Each frame consists of 262 horizontal TV lines and each line is made up of 228 color clocks. The 6502 microprocessor runs at 1.79 MHz. This rate was chosen so that one machine cycle is equivalent in length to two color clocks. One clock is approximately equal in width to two TV lines.
In any graphics mode, the display is divided up into small squares or rectangles called pixels (picture elements). The highest resolution graphics mode has a pixel size of 1/2 color clock by 1 TV line. A sample display list is given in section IV.
The current TV line may be determined by reading the vertical counter (VCOUNT). This register gives the line count divided by 2. There are 262 lines per frame so VCOUNT runs from 0 to 130 (0 to 155 on the PAL system). The 0 point occurs near the end of vertical blank (see figure on the following page). Vertical blank (VBLANK) is the time during which the electron beam returns back to the top of the screen in preparation for the next frame. The ANTIC and GTIA do not do interlacing, so each frame is identical unless the program which is being executed changes the display. Vertical sync (VSYNC) occurs during the fourth through sixth lines of vertical blank (VCOUNT hex 7D through 7F). This tells the TV set where each frame starts. After VSYNC, there are 16 more lines of VBLANK for a total of 22 lines of VBLANK. The display list jump and wait instruction (to be described later) causes the display list graphics to start at the end of VBLANK.
The primary function of the ANTIC chip is to fetch data from memory (independent of the microprocessor) for display on the TV screen. It does this with a technique called "Direct Memory Access" or DMA. It requests the use of the memory address and data bus by sending a signal called HALT to the microprocessor, causing the processor to become "TRI-STATE" (open circuit) all during the next computer cycle. The ANTIC chip then takes over the address bus and reads any data it wishes from memory. Another name for this type of DMA is "cycle stealing". Once initiated, this DMA is completely and automatically controlled by the ANTIC chip without need for further microprocessor intervention.
The ANTIC provides DMA by use of the following register. They are: Character Address register, Player-Missile Base register, Display List Low and High pointer, Character control register, and DMA Control register. The ANTIC also controls vertical and horizontal scrolling. The ANTIC also provides a wait for horizontal sync (WSYNC) command that allows the microprocessor to synchronise itself to the TV horizontal line rate. There are horizontal and vertical light pen registers.
The ANTIC also provides a Non-Maskable Interrupt service to the microprocessor. The microprocessor can read the NMI interrupt status register to determine the cause of interrupt. The status register can be reset by probing a single register.
In addition to a Vertical Blank Interrupt, which allows the microprocessor to synchronize to the vertical TV display, this system also provides a Wait for Horizontal Sync (WSYNC) command that allows the microprocessor to synchronize itself to the TV horizontal line rate. This sync takes effect when the processor writes to an I/0 location called WSYNC, whenever it desires horizontal synchronization. Writing to this address sets a latch which pulls to zero a pin on the microprocessor called READY. When READY goes to zero the microprocessor stops and waits. The latch is automatically reset (returning READY true) at the beginning of the next horizontal blank interval, releasing the microprocessor to resume program execution.
WSYNC (Wait for Horizontal Blank Synchronism – i.e. wait until start of next TV line.)(D40A)
D7 D6 D5 D4 D3 D2 D1 D0 Not used
This address sets a latch that pulls down on the RDY line to the microprocessor, causing it to wait until this latch is automatically reset by the beginning of horizontal blank. Display list interrupts may be delayed by 1 line if WSYNC is used. Used by OS keyboard click routine.
The current TV line may be determined by reading the vertical counter (VCOUNT). This register gives the line count divided by 2. There are 262 lines per frame so VCOUNT runs from 0 to 130 (0 to 155 on the PAL system). The 0 point occurs near the end of vertical blank.
VCOUNT (Vertical Counter)(D40B)
This address reads the Vertical TV Line Counter (8 most significant bits).
D7 D6 D5 D4 D3 D2 D1 D0 V8 V7 V6 V5 V4 V3 V2 V1 V0 V0 not read. Two line resolution supplied.
The primary function of the ANTIC chip is to fetch data from memory (independent of the microprocessor) for display on the TV screen. It does this with a technique called "Direct Memory Access" or DMA. It requests the use of the memory address and data bus by sending a signal called HALT to the microprocessor, causing the processor to become "TRI-STATE" (open circuit) all during the next computer cycle. The ANTIC chip then takes over the address bus and reads any data it wishes from memory. Another name for this type of DMA is "cycle stealing". Once initiated, this DMA is completely and automatically controlled by the ANTIC chip without need for further microprocessor intervention.
There are two types of DMA: Playfield and Player-Missile (see Figure II.2). The playfield DMA control circuit on the ANTIC chip resembles a small dumb microprocessor. By halting the main microprocessor it can fetch its own instructions from memory (the display list) addressed by its program counter(display list pointer). Each instruction defines the type (alpha character or memory map), and the resolution (size of bits on the screen), and the location of the data in memory which is to be displayed on the next group of lines.
In order to begin this DMA the main microprocessor must store a display list of instructions in memory, store data to be displayed in memory, tell the ANTIC where the display list is (initialize the display list pointer) and enable the DMA control flags on the ANTIC (DMACTL register).
In addition to the playfield DMA described above, the ANTIC chip simultaneously controls another DMA channel. This type of DMA addresses PLAYER-MISSILE graphics data stored in memory and passes the graphics data on to the CTIA chip graphics registers. This type of DMA (if enabled) occurs automatically, interspersed with the playfield DMA described previously. This PLAYER-MISSILE DMA has no display list or instructions, and is therefore much simpler than the PLAYFIELD DMA.
In addition to the two types of display DMA, the ANTIC chip also generates DMA addresses for the refresh of the dynamic memory RAM used in this system. This is also completely automatic and need be considered by the programmer only if he is concerned with real-time programming where an exact count of the computer cycles is important.
The player-missile graphic registers may be reloaded by the microprocessor (GRAF(X)), or automatically from meory with direct memory access (DMA) - see figure on next page. The programmer must place the object graphics in memory, write the player-missile base address (PMBASE), and enable player-missile DMA (DMACTL, GRACTL). The transfer of object graphics from memory to display is then fully automatic. GRACTL is a control register on the GTIA chip.
DMACTL (Direct Memory Access Control)(D400)
This address writes data into the DMA Control Register.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| 0 | 0 | No Playfield DMA | ||||||
| 0 | 1 | Narrow Playfield DMA (128 Color Clocks) | ||||||
| 1 | 0 | Standard Playfield DMA (160 Color Clocks) | ||||||
| 1 | 1 | Wide Playfield DMA (192 Color Clocks) | ||||||
| 1 | Enable Missile DMA | |||||||
| 1 | Enable Player DMA | |||||||
| 0 | 2 line P/M resolution | |||||||
| 1 | 1 Line P/M resolution | |||||||
| 1 | Enable instruction fetch DMA | |||||||
| Not used | ||||||||
PMBASE specifies the most significant byte (MSB) of the address of the player-missile graphics. The location of the graphics for each object is determined by adding an offset to PMBASE *256 (decimal). The bytes between the base address and the missile data are not used by ANTIC, so they are available to the programmer.
Only the five most significant bits of PMBASE are used with single-line resolution and the six most significant bits are used with two-line resolution. This means that the location of the graphics in memory is restricted to certain page boundaries. Two-line resolution means that each byte of data is repeated for two lines. (see DMACTL, bit 4). 640 (decimal) bytes (5x128) are required for two-line resolution and 1280 bytes (5x256) for one-line resolution.
Each byte in the player graphics area represents eight pixels which are to be displayed on the corresponding line(s) of the TV screen. A 1 indicates that the player s color-lum is to be displayed in that pixel. The graphics may be anything, not just rectangles like the ones in figure II.3. The player graphics may fill the entire height of the screen or they may be only a couple of lines high if the rest of the display data is all 0's. Each byte in the missile display also represents eight pixels, two pixels for each missile. Each pixel may be 1, 2, or 4 color clocks, and is determined by the SIZE registers.
PMBASE (Player-Missile Address Base Register D407)
This address writes data into the Player-Missile Address Base Register. The data specifies the MSB of the address of the player and missile DMA data (see section II).
1- line resolution
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | PMBASE | ||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
| Base address |
Player Missile select |
Player Missile scan counter |
||||||||||||||
2- line resolution
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | PMBASE | ||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
| Base address |
Player Missile select |
Player Missile scan counter |
||||||||||||||
Playfield is always generated by DMA. There are four playfields, each identified by its own color-lum register and collision detection. Playfield is generated by two different DMA techniques: memory map and character. Both methods provide lists of instructions in memory, independent of the player-missile generation.
Unlike players and missiles, there are no horizontal position registers for playfield. Each player may have only one byte per display line. Playfield on the other hande, may require up to 48 bytes per line because it can fill the entire width of the screen.
There are three different playfield widths: Narrow (128 color clocks), standard (160 colour clocks), and wide (192 color clocks). the width is selected by storing into DMACTL. The advantage of a narrower width is that less RAM is required and fewer machine cycles are stolen for DMA.
The display list is a sequence of display instructions stored in memory. These instructions are either one (1) byte or three (3) bytes long. The display list can be considered a display program, and the Display List Counter that fetches these instructions can be thought of as a display program counter. (10 bit counter plus 6 bit base register.)
The display list counter can be initialized by writing to DLISTH and DLISTL. (or OS shadow registers SDLSTH and SDLSTL). Once initialized this counter value is used to address the display list, fetch the instruction, display one (1) to sixteen (16) lines of data on the TV screen, increment the Display List Counter, fetch the next display instruction, and so on automatically without microprocessor control (see DLISTL and DLISTH). DLISTL and DLISTH should be altered only during vertical blank or when DMA is disabled (see DMACTL).
Each instruction defines the type (alpha character or memory map) and the resolution (size of bits on screen) and the location of data in memory to be displayed for a group (1 to 16) of lines. Each group of lines is called a display block.
THE DISPLAY LIST CANNOT CROSS A 1K BYTE MEMORY BOUNDARY UNLESS A JUMP INSTRUCTION IS USED.
DLISTH MSB DLISTL LSB D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fixed (6 bits) Counter (10 bits)
DISPLAY LIST COUNTER
DLISTL (Display List Low) (D402)
This address writes data into the low byte of the Display List Counter.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Display List Counter Bit Position |
DLISTH (Display List High) (D403)
This address writes data into the high byte of the Display List Counter.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | Display List Counter Bit Position |
The display list is a sequence of display instructions stored in memory. These instructions are addressed byt the Display List Counter. Loading these registers defines the address of the beginning of the Display List (See Sections I and II).
Note: The top 6 bits are latches only and have no count capability, therefore the display list cannot cross a 1K memory boundary unless a jump instruction is used.
DLISTL and DLISTH should be changed only during the vertical blank or with DMA disabled. Otherwise, the screen may roll. Bit 7 of NMIEN must be set in order to receive display list interrupts.
Each instruction consists of either an opcode only, or of an opcode followed by two (2) bytes of operand.
0pcode Single Byte Display Instruction 0pcode Triple Byte Display Instruction Operand Operand
The opcode is always fetched first and placed in the Instruction Register. This opcode defines the type of instruction (1 or 3 bytes) and will cause two more bytes to be fetched if needed. If fetched, these next two (2) bytes will be placed in the Memory Scan Counter, or in the Display List Counter (if the instruction is a Jump).
This register is loaded with the opcode of the current display list instruction. It cannot be accessed directly by the programmer. There are three basic types of display list instructions: blank, jump, and display.
| Blank | D7 | D6 | D5 | D4 | 0 | 0 | 0 | 0 | |
| (1-byte) | This instruction is used to create 1 to 8 blank lines on the display (background color). | ||||||||
| 0 | 0 | 0 | 0 | Blank | |||||
| 0-7 = 1-8 blank lines | |||||||||
| 1 = display list instruction interrupt | |||||||||
| Jump | D7 | D6 | X | X | 0 | 0 | 0 | 1 | |
| (3-bytes) | This instruction is used
to reload the Display List Counter. The next two bytes specify the address to be loaded (LSB first). |
||||||||
| 0 | 0 | 0 | 1 | Jump | |||||
| X | X | Don't care | |||||||
| 0 | Jump (creates one blank line on display) | ||||||||
| 1 | As above then wait until end of next vertical blank | ||||||||
| 1 = display list instruction interrupt | |||||||||
| Display | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| (1 or 3 bytes) | Display mode 2 to F (character or graphics, see later) | ||||||||
| 1 = Horizontal Scroll Enable | |||||||||
| 1 = Vertical Scroll Enable | |||||||||
| 0 = 1-byte instruction, 1 = 3-byte instruction. | |||||||||
| 1 = display list instruction interrupt | |||||||||
Bit 7 of a display list instruction can be set to create a display list interrupt if bit 7 of NMIEN is set. The display list interrupt code can change the colors or graphics during the middle of the TV display. The type of interrupt is determined by checking NMIST. NMIRES clears NMIST.
Bits 5 and 4 of a display type of display list instructions are used to enable vertical and horizontal scrolling. The amount of scrolling depends on the values in the VSCROL and HSCROL registers (to be described later).
Figure II.3: DISPLAY INSTRUCTION OPCODES
This counter is not directly accessible by the programmer. It is loaded with the value in the last 2 bytes of a 3 byte (non-Jump) instruction.
This counter points to the location (address) in memory of data to be directly displayed (memory map display) or to the location of character name strings to be indirectly displayed (character display).
A single byte instruction does not reload this counter. This implies a continuation in memory of data to be displayed from that displayed by the previous instruction. Since this counter really consists of 4 bits of register and 12 of actual counter, a continuous memory block cannot cross 4K byte memory boundaries, unless the counter is repositioned with a 3-byte Load Memory Scan Counter instruction.
MSB third byte of 3 byte instruction LSB Second byte of 3 byte instruction D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fixed (4 bits) Counter (12 bits)
<Pages 27-33 inclusive were missing from the pdf documents thus these are assumed to have been the basis for text used in other Atari documents. The display list example and cycle counting text exist, but the light pen and and NMI Interrupt text sections have not been found.>
<This was described on the missing page 31>
<This was described on the missing page 31>
<interesting but not too relevant to logic>
The
The
INPUT TIMING
(VDC = 5V ± 5% TA = 0ºC to
70ºC)
| Parameter | Note | Signal type | Symbol | Min | Max | Unit | |
| R/!W setup time | BLE Ø2 | TRWS | 130 | ns | |||
| R/!W hold time | ATE Ø2 | TRWH | 30 | ||||
| Address setup time | A0-A3, A8-A15 | BLE Ø2 | TADS | 130 | |||
| Address hold time | ALE Ø2 | TADH | 30 | ||||
| Data setup time | D0-D7 | BTE Ø2 | TDSW | 50 | |||
| Data hold time | ATE Ø2 | TDHW | 10 | ||||
| Data setup time | |RNMI | BTE Ø2 | TDS | 50 | |||
| Data hold time | ATE Ø2 | TDH | 10 | ||||
| Data setup time | !RES | BTE OSC | TDS | 50 | |||
| Data hold time | ATE OSC | TDH | 130 | ||||
| Data setup time | !LP | 4 | BTE Ø2 | TDS | 50 | ||
| BLE Ø2 | TDH | 50 | |||||
| Data hold time | !LP | ATE Ø2 | TDS | 850 | |||
| ALE Ø2 | TDH | 850 | |||||
OUTPUT TIMING
(VDC = 5V ± 5% TA = 0ºC to 70ºC)
| Parameter | Note | Signal type | Symbol | Min | Max | Unit | |
| R/!W setup time | 2 | ATE Ø2 | TRWS | 230 | ns | ||
| R/!W hold time | TRWH | 23 | |||||
| Address setup time | A0-A15 | 2 | ATE Ø2 | TADS | 145 | ||
| Address hold time | TADH | 14 | |||||
| Data setup time | D0-D7 | 3 | ALE Ø2 | TDSW | 185 | ||
| Data hold time | ATE Ø2 | TDHW | 10 | ||||
| Data setup time | !HALT, !NMI | 2 | ATE Ø2 | TDS | 350 | ||
| Data hold time | TDH | 35 | |||||
| Data setup time | RDY | 2 | ATE Ø2 | TDS | 180 | ||
| Data hold time | TDH | 18 | |||||
| Data setup time | !REF | 2 | ATE Ø2 | TDS | 150 | ||
| Data hold time | TDH | 15 | |||||
| Data setup time | AN0-AN2 | 1 | ALE FØ0 | TDS | 195 | ||
| Data hold time | TDH | 19 | |||||
Note:
<>
The
<diagram>
<diagram>
| Write | Read | |||
| Address | Name | Description | Name | Description |
| D400 | DMACTL | DMA Control | ||
| D401 | CHACTL | Character Control | ||
| D402 | DLISTL | Display list pointer Low | ||
| D403 | DLISTH | Display list pointer High | ||
| D404 | HSCROL | Horizontal scroll | ||
| D405 | VSCROL | Vertical scroll | ||
| D406 | ||||
| D407 | PMBASE | Player/Missile base address | ||
| D408 | ||||
| D409 | CHBASE | Character base address | ||
| D40A | WSYNC | Wait for horizontal blank synchronization | ||
| D40B | VCOUNT | Vertical line counter | ||
| D40C | PENH | Light pen Horizontal position | ||
| D40D | PENV | Light pen Vertical position | ||
| D40E | NMIEN | Non-maskable interrupt (NMI) enable | ||
| D40F | NMIRES | Reset for NMIST | NMIST | NMI status |
| D410 /\ || || || \/ D4FF |
Repeated 15 times as above | |||
<already well documented elsewhere>
<big picture of chip and bond wires here. Not very useful>