GTIA

CO14805 (NTSC)

[added comments to original text shown in light purple]

Table of Contents

  1. General
  2. Color-luminance control
  3. Priority Control
  4. Player-Missile Control
  5. Collision
  6. NTSC/PAL register
  7. Trigger inputs
  8. Switch I/O
  9. Electrical Parameters
    1. General
    2. DC & Operating Characteristics
    3. Dynamic Operating Characteristics
    4. I/O Timing
    5. Write I/O Timing
    6. Read I/O Timing

Table of illustrations

  1. DMA timing for the GTIA
  2. GTIA Address table
  3. GTIA Pin List
  4. GTIA Bonding diagram
  5. GTIA MOS Logic

  1. General

    The GTIA performs color-luminance control, player-missile control, priority control, collision detection, and miscellaneous I/O functions.

    There are 9 color-luminance registers. There is one color-luminance register for each player-missile, playfield type and background. When two or more color-luminance overlap there must be a decision made as to which object will have priority. This is done by hardware with a priority register to select which group of objects have priority over other objects.

    The GTIA has a horizontal position register for each player and missile. It also has a size control register for each player and a single graphic register for the missiles. There is a graphic register for each player and a single register for the missiles. There is a collision detect between all players, missiles and playfield. However, there is no collision detect between each playfield.

    There are four trigger inputs and four bi-directional I/O pins for miscellaneous I/O functions. There are three inputs that receive data from the ANTIC to generate the playfield graphics and sync the GTIA with the ANTIC.

  2. Color-luminance control

    A color-luminance register is used on the GTIA chip for each player-missile and playfield type. Each color-luminance register is loaded by the microprocessor with a code representing the desired color and luminance of its corresponding player-missile or playfield type. As the serial data of the different object pass through the GTIA, it is "impressed" with the color and luminance values in these registers. Therefore, when a player, missile or playfield is turned on, the corresponding color and luminance will be turned on. To prevent two color-luminances from fighting, priority is established. See section 3 for Priority.

    These addresses write data to the following registers:

    Color-lum of player-missile 0 (COLPM0) Address = 12
Color-lum of player-missile 1 (COLPM1) Address = 13
Color-lum of player-missile 2 (COLPM2) Address = 14
Color-lum of player-missile 3 (COLPM3) Address = 15
Color-lum of playfield 0      (COLPF0) Address = 16
Color-lum of playfield 1      (COLPF1) Address = 17
Color-lum of playfield 2      (COLPF2) Address = 18
Color-lum of playfield 3      (COLPF3) Address = 19
Color-lum of background       (COLBK)  Address = 1A
    D7 D6 D5 D4 D3 D2 D1 D0  
                  X Not used
    0 0 0   Zero luminance (black)
    0 0 1    
    etc.    
    1 1 1   Max luminance (white)
    0 0 0 0 Grey
    0 0 0 1 Gold
    0 0 1 0 Orange
    0 0 1 1 Red-orange
    0 1 0 0 Pink
    0 1 0 1 Purple
    0 1 1 0 Purple-Blue
    0 1 1 1 Blue
    1 0 0 0 Blue
    1 0 0 1 Light Blue
    1 0 1 0 Turquoise
    1 0 1 1 Green-Blue
    1 1 0 0 Green
    1 1 0 1 Yellow-Green
    1 1 1 0 Orange-Green
    1 1 1 1 Light Orange

  3. Priority Control

    Priority (PRIOR) Address = 1B

    When moving objects such as players, missiles and playfield overlap on the TV screen, a decision must be made as to which object shows in front of the other. Objects which appear to pass in front of other objects are said to have priority over them. Priority is assigned to each object by the GTIA chip before the serial data from each object are combined with the other chip before the serial data from each object are combined with the other objects and sent out to the TV screen. Setting the priority is done by writing from the microprocessor to the GTIA priority control register (PRIOR).

    D7 D6 D5 D4 D3 D2 D1 D0 Priority:
            0 0 0 1
    P0
    P1
    P2
    P3    		 Highest
    PF0
    PF1
    PF2
    PF3 + P5    		  
    BAK Lowest
    0 0 1 0
    P0
    P1    		 Highest
    PF0
    PF1
    PF2
    PF3 + P5    		  
    P2
    P3    		  
    BAK Lowest
    0 1 0 0
    PF0
    PF1
    PF2
    PF3 + P5    		 Highest
    P0
    P1
    P2
    P3    		  
    BAK Lowest
    1 0 0 0
    PF0
    PF1    		 Highest
    P0
    P1
    P2
    P3    		  
    PF2
    PF3 + P5    		  
    BAK Lowest
      NOTE:
      The use of priority bits in a "non-exclusive" mode (more than 1 bit true) will result in objects (whose priorities conflict) turning BLACK in the overlap region.
    EXAMPLE: PRIOR code = 1010.
    This will black P0 or P1 if they are over PF0 or PF1.
    It will also black P2 or P3 if they are over PF2 or PF3.

    The priority control register also controls the fifth player. The fifth player is the combination of all four missiles and shown as playfield 3 color-lum. However, there is no priority between playfields. Therefore, the fifth player would have no priority between playfields.

    D4   Fifth Player Enable
        This bit causes all missiles to assume the color of Playfield Type 3 (COLPF3). This allows missiles to be positioned together with a common color for use as a fifth player.
    D5   Multiple Color Player Enable
        This bit causes the logical "or" function of the bits of the colors of Player 0 with Player 1 and also of Player 2 with Player 3. This permits overlapping the position of two players with a third player in the overlapped region.

    The priority control register also controls playfield data interpretation from the ANTIC. There are four modes. They are: four color-lum (normal CTIA mode), 1 color - 16 lum (GTIA), 9 color-lum (GTIA), and 16 color- 1 lum (GTIA).
      GTIA Playfield modes
    0 0   Normal No GTIA mode ( CTIA operation)
    0 1   1 color - 16 luminances mode
    1 0   9 color-luminances mode
    1 1   16 color- 1 luminance mode

    In the normal mode, the GTIA will interpret the AN0-AN2 data from ANTIC as:

    AN  
    2 1 0
    0 0 0 Background colour
    0 0 1 Vertical sync
    0 1 0 Horizontal blank and clear 40-character mode
    0 1 1 Horizontal blank and set 40-character mode
    1 0 0 Playfield 0
    1 0 1 Playfield 1
    1 1 0 Playfield 2
    1 1 1 Playfield 3

    Refer to the ANTIC data sheet for normal ANTIC display of playfield.

    NOTE: If the GTIA is in the 40-character mode, there is no priority betweeen playfield 1 luminance and all player-missile luminances.

    In the 1-color 16-luminances mode, the GTIA will interpret the AN0-AN2 data from ANTIC as:

    AN  
    2 1 0
    0 0 0 Background colour
    0 0 1 Vertical sync
    0 1 0 Horizontal blank and clear 40-character mode
    0 1 1 Horizontal blank and set 40-character mode
    1 D3 D2 Playfield 0
    1 D1 D0 Playfield 1

    Note: Dn indicates data

    In the 16-lum mode, it takes 2 color clocks to make one playfield pixel. The ANTIC will send the AN2 to AN0 data every color clock. At the beginning of a pixel, lum D3 and lum D2 are loaded for the next pixel and on the second color clock, lum D1 and lum D0 are loaded for the next pixel. The background color register is used for the playfield color and the background lum register is 'ORed' with lum D3 D2 D1 D0 for playfield luminance. Therefore, zero should be loaded into background luminance in this mode.

    In the 9-color-lum mode, the GTIA will interpret the AN0-AN2 data from ANTIC as:

    AN  
    2 1 0
    0 0 0 Background colour
    0 0 1 Vertical sync
    0 1 0 Horizontal blank and clear 40-character mode
    0 1 1 Horizontal blank and set 40-character mode
    1 D3 D2 Playfield 0
    1 D1 D0 Playfield 1

    Note: Dn indicates data

    In the 9-color-lum mode, it takes 2 color clock to make one playfield pixel. The ANTIC will send the AN2 to AN0 data every color clock. At the beginning of a pixel, lum D3 and lum D2 are loaded for the next pixel and on the second color clock, lum D1 and lum D0 are loaded for the next pixel. The data word D3 to D0 determines one of the nine color-lum registers for that pixel. See the table below for data to color register assignment.

    D3 D2 D1 D0  
    0 0 0 0 Color-lum of player-missile 0
    0 0 0 1 Color-lum of player-missile 1
    0 0 1 0 Color-lum of player-missile 2
    0 0 1 1 Color-lum of player-missile 3
    X 1 0 0 Color-lum of playfield 0
    X 1 0 1 Color-lum of playfield 1
    X 1 1 0 Color-lum of playfield 2
    X 1 1 1 Color-lum of playfield 3
    1 0 X X Color-lum of background

    Note X indicates "Don't cares".

    In the 16-color - 1 lums mode, the GTIA will interpret the AN0-AN2 data from ANTIC as:

    AN  
    2 1 0
    0 0 0 Background colour
    0 0 1 Vertical sync
    0 1 0 Horizontal blank and clear 40-character mode
    0 1 1 Horizontal blank and set 40-character mode
    1 D3 D2 Playfield 0
    1 D1 D0 Playfield 1

    Note: Dn indicates data

    In the 16-color mode, it takes 2 color clocks to make one playfield pixel. The ANTIC will send the AN2 to AN0 data every color clock. At the beginning of a pixel, color D3 and lum D2 are loaded for the next pixel and on the second color clock, color D1 and lum D0 are loaded for the next pixel. The background luminance register is used for the playfield luminance and the background color register is 'ORed' with color D3 D2 D1 D0 for playfield color. Therefore, zero should be loaded into background color in this mode.

  4. Player-Missile Control

    The players and missiles are small objects which can be moved quickly in the horizontal direction by changing their position registers. They are called players and missiles because they were originally designed to be used in games for objects such as aeroplanes and bullets.However, there are many other possible applications for them. The four player-missile color registers, in conjunction with the four playfield registers and background color register, make it possible to display 9 different colors at the same time.

    There are a total of four players and four missiles. The four missiles may be grouped together and used as a fifth player. These objects are positioned horizontally by eight horizontal position registers (HPOS(X)). These registers may be relocated at any time by the processor, allowing an object to be replicated many times across a horizontal TV line.

    Player horizontal position:

    HPOSP0 (Player  0) address = 00
HPOSP1 (Player  1) address = 01
HPOSP2 (Player  2) address = 02
HPOSP3 (Player  3) address = 03
HPOSM0 (Missile 0) address = 04
HPOSM1 (Missile 1) address = 05
HPOSM2 (Missile 2) address = 06
HPOSM3 (Missile 3) address = 07

    These addresses write data into the player or missile horizontal position register. The horizontal position value determines the color clock location of the left edge of the object. Hex 30 is the left edge of the standard width screen. Hex D0 is the right edge of the standard width screen.

    D7 D6 D5 D4 D3 D2 D1 D0

    The shape of a player or missile is determined by the value in the graphics register. The players have independent eight-bit graphics registers. These registers may be reloaded at any time by the microprocessor, though they are usually changed during horizontal blank time. The data in these graphics registers are placed on the display whenever the horizontal counter equals the corresponding horizontal position registers. The same data will be displayed every line unless the graphic registers are reloaded with new data. These player-missile graphic registers may also be reloaded automatically from memory with direct memory access (DMA). To use DMA for the player-missile graphics, !HALT input must go low during horizontal blank. From the falling edge of !HALT, the GTIA will pull the graphic data from the data bus, if they are enabled by GRACTL. However, the GTIA does not address the data. This is done by ANTIC. See the ANTIC data sheet for use of DMA.

    GRACTL (Graphics control register) Address = 1D

    X X X X X D2 D1 D0
          1 Enable latches on TRIG0 - TRIG3 inputs
      Latches are cleared and TRIG0 - TRIG3 act as normal inputs when this control bit is zero.
    1   Enable Player DMA to Player Graphics Registers
    1     Enable Missile DMA to Missile Graphics Registers
           
            Not used

    DMA is enabled by setting both DMACTL (ANTIC) and GRACTL(GTIA). Setting the DMACTL only will result in cycles to be stolen but no display will be generated for players or missiles.

    Graphics register:
    GRAFP0 (Player 0 graphic register) Address = 0D
    GRAFP1 (Player 1 graphic register) Address = 0E
    GRAFP2 (Player 2 graphic register) Address = 0F
    GRAFP3 (Player 3 graphic register) Address = 10

    D7 D6 D5 D4 D3 D2 D1 D0
    Left Right

    GRAFM (Missile graphic register) Address = 11

    D7 D6 D5 D4 D3 D2 D1 D0  
    L R L R L R L R  
    M3 M2 M1 M0  

    These addresses write data into the player graphic register, independent of DMA. These registers may also be accessed by DMA.

    DMA Timing for GTIA

      Ø2   !HALT   D7-D0  
      0   1      
    1      
    0   0
    1      
    0   0
    1   Missile
    Graphic    		  
    0
    1      
    0
    1   Player 0
    Graphic    		  
    0
    1   Player 1
    Graphic    		  
    0
    1   Player 2
    Graphic    		  
    0
    1   Player 3
    Graphic    		  
    0
    1      
    0

    Note: GTIA does not address the data, but only looks for the data.
    [time axis runs from top to bottom of this diagram.]

    [Text to be added]

  5. Collision

    These collision registers can be cleared by writing to a single register.
    A collision registers are cleared by when this is done.

    HITCLR (Collision, "hit" clear) Address = 1E

    D7 D6 D5 D4 D3 D2 D1 D0
    Not used

  6. NTSC/PAL register

    There are two versions of the GTIA: The NTSC (United States TV standard) and PAL (one of the European TV standards). The PAL GTIA has been designed so that most programs will run without modification. However, some differences may be noticeable. There is a hardware register (PAL) which a program can read to determine whether it is PAL or NTSC and adjust accordingly.

    PAL (NTSC/PAL register) Address = 14

    D7 D6 D5 D4 D3 D2 D1 D0  
    X X X X       X Not used
      1 1 1   NTSC (US TV)
      0 0 0   PAL (European TV)

    [The SECAM data sheet says that all 'not used' bits are read as zero on D7-4 and as one on D3-0. Thus the register above reads hex 0F for NTSC and 01 for PAL and SECAM.]

  7. Trigger inputs

    There are four inputs (T0-3) that have been used as the inputs to sense the trigger buttons of the joystick controller. These inputs are normally read directly by the microprocessor reading TRIG 0 through TRGI3. However, if bit 2 of GRACTL is set to a logic high, these inputs are latched whenever they go to a logic zero. These latches are reset (true) when bit 2 of GRACTL is set to a logic zero.

    TRIG0 (Trigger 0 input) Address = 10
    TRIG0 (Trigger 1 input) Address = 11
    TRIG0 (Trigger 2 input) Address = 12
    TRIG0 (Trigger 3 input) Address = 13

    D7 D6 D5 D4 D3 D2 D1 D0  
      0 Trigger button pressed
      1 Trigger button not pressed
        Not used (zero forced)

  8. Switch I/O

    There are four I/O pins (S0-3) that have been used as switch inputs. This port can be read a single address which puts the data directly on the data bus. When this address is written to, the data going out of the port is inverted from the data on the data bus. The inputs have internal pull-up resistance to VDD. The outputs are open-drain. If the I/O port is to be used as inputs then zero should be written to CONSOL register.

    CONSOL (Switch port) Address = 1F

    D7 D6 D5 D4 D3 D2 D1 D0  
      S3 S2 S1 S0  
              Not used (zero forced)

  9. Electrical Parameters

    [interesting but not too relevant to logic]

    1. General

    2. DC & Operating Characteristics

    3. Dynamic Operating Characteristics

      INPUT TIMING
      (VDC = 5V ± 5% TA = 0ºC to 70ºC)

      Parameter Note Signal type Symbol Min Max Unit
                   

      OUTPUT TIMING
      (VDC = 5V ± 5% TA = 0ºC to 70ºC)

      Parameter Note Signal type Symbol Min Typ Max Unit
      Data setup time D0-D7 3 ATE Ø2 TDSR     50 ns
      Data hold time ATE Ø2 TDHR 20    
      Data setup time !CSYNC 1 ATE OSC TDS     400
      Data hold time ATE OSC TDH 40    
      Data setup time L0-L3 1 ALE OSC TDS     450
      Data hold time ALE OSC TDH 45    
      Data setup time S0-S3 2 ATE Ø2 TDS     800
      Data hold time ATE Ø2 TDH 80    
      COLOR DELAY LINE OUTPUT
      NOTE: Output is OPEN DRAIN and
      pull-up affects leading edge delay
      OUTPUT DELAY TIME
      with VDEL (pin 17) = 7.0V and      		 1 ATE OSC TDD        
      WITH COLOR = C3..0              
      0000 (no color out)              
      0001           167 ns
      0010           188
      0011           209
      0100           230
      0101           251
      0110           272
      0111           293
      1000           314
      1001           335
      1010           356
      1011           377
      1100           398
      1101           419
      1110           440
      1111           461
      COLOR DELAY LINE OUTPUT
      OUTPUT DELAY TIME
      with VDEL (pin 17) = 5.0V and      		 1 ATE OSC TDD        
      WITH COLOR = C3..0              
      0000 (no color out)              
      0001         190 190 ns
      0010         209 225
      0011         227 260
      0100         246 295
      0101         264 330
      0110         283 365
      0111         302 400
      1000         320 435
      1001         339 470
      1010         358 505
      1011         376 540
      1100         395 575
      1101         413 610
      1110         432 645
      1111         451 680
      COLOR SELECT DELAY 1 ATE OSC TDD     610 ns
                     

      [VDEL is a voltage that controls the colour delay line step size: either (146 + n * 21) ns or (155 + n * 35) ns.
      Since the master crystal oscillator runs with a period of about 279 ns, this delay cannot be clocked digital logic.
      There may be some analogue delay line circuit within the GTIA.
      The apparent design intention is that there are 15 colours equally spaced in 24° steps around the 360° of possible phase shifts. One fifteenth of the colour carrier period is 18.62433862 ns for NTSC.]

    4. I/O Timing

           ->|      |<---- BLE (BEFORE LEADING EDGE)
         ---->|     |<--- ALE (AFTER LEADING EDGE)
              |          -->|    |<-- BTE (BEFORE TRAILING EDGE)
              |              --->|     |<--- ATE (AFTER TRAILING EDGE)
              |                  |
              |                  |
              | |<---THI------>| |
              | |              | |                             / / 
        2.4V--->/              \ |                  /         / /  \
PH2 or OSC     /|              |\                  /|              |\
              / |              | \                / |              | \
      0.8V-->/  |              |  \ /  /         /  |              |  \    
             |  |              |  |/  /          |  |              |  |    
       TR--->|  |        TF--->|  |<--           |  |              |  |    
             |  |              |  |              |  |              |  |    
TE OUTPUT:   |  |             --->|          |<--- TDS        TDH --->|  |<-- 
             |  |              |  |          |   |  |              |  |  | 
             |  |              |  |          |   |  |          / / |  |  |      
//////////////////////////////////////////\  /                / /          \  //
///////////////////////////////////////////\/ VALID                         \///
////////////////////////////////////////////\                               /\//
///////////////////////////////////////////  \                 / /         /  \/
             |  |              |  |              |  |         / /  |  |    
             |  |              |  |              |  |              |  |    
LE OUTPUT:   |  |              |  |              |  |              |  |    
            --->|          |<--- TDS        TDH --->|  |<-- 
             |  |          |   |  |              |  |  |
             |  |          |   |  | / /          |  |  |    
////////////////////////\  /       / /                 \  //
/////////////////////////\/ VALID                       \///
//////////////////////////\                             /\//
/////////////////////////  \        / /                /  \/
             |  |              |  |/ /           |  |
LE OUTPUT:   |  |              |  |              |  |
      [more of this diagram to follow]

    5. Write I/O Timing

      [diagram]

    6. Read I/O Timing

      [diagram]