WSYNC
This address halts microprocessor by clearing the RDY latch to a zero. RDY is set true again by the leading edge of horizontal blank.
D7 D6 D5 D4 D3 D2 D1 D0 Data bits not used
RSYNC
This address resets the horizontal sync counter to define the beginning of horizontal blank time, and is used in chip testing.
D7 D6 D5 D4 D3 D2 D1 D0 Data bits not used
VSYNC
This address controls the vertical sync time by writing D1 into the VSYNC latch.
D7 D6 D5 D4 D3 D2 D1 D0 Not used 1 Start vertical sync 0 Stop vertical sync
VBLANK
This address controls the vertical blank and the latches and dumping transistors on the input port by writing into bits D7, D6 and D1 of the VBLANK register.
D7 D6 D5 D4 D3 D2 D1 D0 Not used 1 Start vertical blank 0 Stop vertical blank 1 Enable I4, I5 latches Note: Disable latches (D6=0) also
resets latches to logic true.0 Disable I4, I5 latches 1 Dump I0, I1, I2, I3 ports to ground 0 Remove dump path to ground
PF0 (PF1, PF2)
These addresses are used to write into the playfield registers.
D7 D6 D5 D4 D3 D2 D1 D0 PF0
D7 D6 D5 D4 D3 D2 D1 D0 PF1
D7 D6 D5 D4 D3 D2 D1 D0 PF2 Playfield Registers Serial Output
1 Horizontal Line (160 Clocks) Playfield
Reflect
Control4-7 7-0 0-7 4-7 7-0 0-7 REF = 0 PF0 PF1 PF2 PF0 PF1 PF2 > < Each bit
= 4 clocks.4-7 7-0 0-7 7-0 0-7 7-4 REF = 1 PF0 PF1 PF2 PF2 PF1 PF0 >| |< Center
CTRLPF
This address is used to write into the Playfield Control Register (a logic 1 causes action as described below).
D7 D6 D5 D4 D3 D2 D1 D0 Not used REF (Reflect Playfield) SCORE (Left half of Playfield gets color of player 0, right half of Playfield gets color of player 1. PFP (Playfield gets priority over players so they move behind Playfield) Ball size: 0 0 1 clock 0 1 2 clocks 1 0 4 clocks 1 1 8 clocks
NUSIZ0 (NUSIZ1)
These addresses control the number and size of players and missiles.
D7 D6 D5 D4 D3 D2 D1 D0 Player-Missile number and size <-- one television line (160 clocks) --> 0 0 0 > 8 < One copy 0 0 1 Two copies, close 0 1 0 Two copies, medium 0 1 1 Three copies, close 1 0 0 Two copies, wide 1 0 1 Double width player 1 1 0 Three copies, medium 1 1 1 Quad width player Not used Missile size (width) 0 0 1 clock 0 1 2 clocks 1 0 4 clocks 1 1 8 clocks Not used
RESP0 (RESP1, RESP2, RESM1, RESBL)
These addresses are used to reset players, missiles and the ball. The object will begin its serial graphics at that time of a horizontal line at which the reset address occurs.
D7 D6 D5 D4 D3 D2 D1 D0 Data bits not used
RESMP0 (RESMP1)
These addresses are used to reset the horizontal location of a missile to the center of its corresponding player. As long as this control bit is true the missile will remain locked to the centre of its player and the missile graphics will be disabled.
When a zero is written to this location the missile is enabled, and can be moved independently of the player.
D7 D6 D5 D4 D3 D2 D1 D0 Not used RESMP (Missile-Player Reset)
HMOVE
This address causes the horizontal motion register values to be acted upon during the horizontal blank time in which it occurs. It must occur at the beginning of horizontal blank in order to allow time for generation of extra clock pulses into the horizontal position counters. If motion is desired this command must immediately follow a hsync command in the program.
D7 D6 D5 D4 D3 D2 D1 D0 Data bits not used
HMCLR
This address clears all horizontal motion register to zero (no motion).
D7 D6 D5 D4 D3 D2 D1 D0 Data bits not used
HMP0 (HMP1, HMM0, HMM1, HMBL)
These addresses write data (horizontal motion values) into the horizontal motion registers. These registers will cause horizontal motion only when commanded to do so by the horizontal move command HMOVE. The motion values are coded as shown below.
D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 +7 Move
left
indicated
number
of
clocks0 1 1 0 +6 0 1 0 1 +5 0 1 0 0 +4 0 0 1 1 +3 0 0 1 0 +2 0 0 0 1 +1 0 0 0 0 0 No motion 1 1 1 1 -1 Move
right
indicated
number
of
clocks1 1 1 0 -2 1 1 0 1 -3 1 1 0 0 -4 1 0 1 1 -5 1 0 1 0 -6 1 0 0 1 -7 1 0 0 0 -8
Note: These motion registers should not be modified during the
24 cycles immediately following an HMOVE command.
Unpredicatable motion values may result.
ENAM0 (ENAM1, ENABL)
These addresses write D1 into the 1-bit Missile or Ball Graphics registers.
D7 D6 D5 D4 D3 D2 D1 D0 Not used 1 Disables object 0 Enables object
GRAPO (GRP1)
These addresses write data into the Player Graphics Registers
D7 D6 D5 D4 D3 D2 D1 D0 (See COLBK for bit assignments) Left Right Player on TV Screen Player Graphics Serial Output
<- one television line (160 clocks) -> Player reflect control ........ 7......0 REFP0 = 0 GRP0 0......7 REFP0 = 1 ->| |<-- serial output begins
when position counter
crosses zero(REFP1 acts
in the same way
on GRP1 output)
REFP0 (REFP1)
These addresses write data into the 1-bit Player Reflect Registers
D7 D6 D5 D4 D3 D2 D1 D0 Not used 0 No Reflect (D7 of GRP on left) 1 Reflect (D0 of GRP on left) Not used
VDELP0 (VDELP1, VDELBL)
These addresses write data into the 1-bit Vertical Delay Registers, to delay players or ball by one vertical line.
D7 D6 D5 D4 D3 D2 D1 D0 0 No delay 1 Delay Not used
CXCLR
This address clears all collision latches to zero (no collision).
D7 D6 D5 D4 D3 D2 D1 D0 Data bits not used
COLUP0 (COLUP1, COLUPF, COLUBK)
These addresses write data into the Player, Playfield and Background Color-Lum Registers.
D7 D6 D5 D4 D3 D2 D1 D0 X Not used luminance 0 0 0 Black 0 0 1 Dark grey 0 1 0 0 1 1 Grey 1 0 0 1 0 1 1 1 0 Light Grey 1 1 1 White 0 0 0 0 None 0 0 0 1 Gold 0 0 1 0 Orange 0 0 1 1 Red-orange 0 1 0 0 Pink 0 1 0 1 Purple 0 1 1 0 Purple-Blue 0 1 1 1 Blue 1 0 0 0 Blue 1 0 0 1 Light Blue 1 0 1 0 Turquoise 1 0 1 1 Green-Blue 1 1 0 0 Green 1 1 0 1 Yellow-Green 1 1 1 0 Orange-Green 1 1 1 1 Light Orange
AUDF0 (AUDF1)
These addresses write data into each of the four Audio Frequency Control Registers.
D7 D6 D5 D4 D3 D2 D1 D0 30 kHz divided by 0 0 0 0 0 1 (no division) 0 0 0 0 1 2 etc. 1 1 1 1 0 31 1 1 1 1 1 32
AUDC0 (AUDC1)
These addresses write data into the Audio Mode Control Registers which control the noise content and additional division of the audio output.
D7 D6 D5 D4 D3 D2 D1 D0 HEX Type of noise or division: 0 0 0 0 0 Set to 1 (volume only) 1 0 0 0 1 4 bit poly 2 0 0 1 0 ÷ 15 bit poly --> 4 bit poly 3 0 0 1 1 5 bit poly --> 4 bit poly 4 0 1 0 0 ÷ 2 5 0 1 0 1 ÷ 2 6 0 1 1 0 ÷ 31 7 0 1 1 1 5 bit poly --> ÷ 2 8 1 0 0 0 9-bit poly (white noise) 9 1 0 0 1 5-bit poly A 1 0 1 0 ÷ 31 B 1 0 1 1 Set last 4 bits to 1 C 1 1 0 0 ÷ 6 D 1 1 0 1 ÷ 6 E 1 1 1 0 ÷ 93 F 1 1 1 1 5-bit poly ÷ 6
Noise Content or Distortion, and Volume
These addresses write data into the Audio Volume Control Registers which set the pull-down impedance driving the audio output pads.
D7 D6 D5 D4 D3 D2 D1 D0 volume: 0 0 0 0 No output current 0 0 0 1 Lowest 0 0 1 0 etc 1 1 1 0 1 1 1 1 Highest